1. Field of the Invention
The present invention relates to a manufacturing method for an epitaxial wafer using a vapor phase growth system.
2. Related Art
An epitaxial wafer is a semiconductor wafer in which an epitaxial layer is grown on a main surface thereof. Recently, there is a demand for epitaxial wafers having high flatness and high definition is required accompanying increased integration of semiconductor devices and design rule miniaturization (miniaturized pattern). A vapor phase growth system that grows an epitaxial layer on a main surface of a semiconductor wafer is used for manufacturing an epitaxial wafer.
With the vapor phase growth system, an epitaxial layer can be grown on a main surface of a semiconductor wafer according to the following steps, for example. First, a semiconductor wafer is placed on a disk-shaped susceptor provided inside a reaction container. Here, an upper face of the susceptor is a concave shaped wafer-placing portion. The reaction container used is configured so that reactant gas can be supplied thereinto. Thereafter, the semiconductor wafer is heated by a heater disposed on an outer surface of the reaction container in order to react the semiconductor wafer with the reactant gas that passes through the inside of the reaction container, thereby growing an epitaxial layer on a main surface of the semiconductor wafer.
However, in growing the epitaxial layer on the main surface of the semiconductor wafer, the epitaxial layer tends to be grown in an outer peripheral portion of a back surface of the semiconductor wafer. In a case where an epitaxial layer is formed between the semiconductor wafer and the susceptor, contact trace of the susceptor (sticking) may remain in the outer peripheral portion of the back surface of the semiconductor wafer.
Furthermore, if such sticking occurs between the back surface of the semiconductor wafer and the susceptor, distortions on the back surface of the semiconductor wafer may be generated due to difference in thermal expansion between the semiconductor wafer and the susceptor when temperature of the heater rises and falls and when the heater is in a high temperature state. Such distortions may lead to pattern displacement in a random orientation, which is difficult to correct, in thermal processing before the photolithography processing of the semiconductor wafer, in a production process of a semiconductor device. There has been a problem in that such pattern displacement further leads to misalignment in photolithography processing.
Given this, a method is proposed for evaluating a surface configuration of an epitaxial wafer by measuring surface configuration of a main surface and a back surface of the epitaxial wafer along a radial direction thereof, calculating a reference line from a predetermined region in surface configuration data thus measured, and obtaining a local slope representing a difference between the reference line and the surface configuration data in a thickness direction (for example, see Japanese Unexamined Patent Application Publication No. 2006-5164).
However, Japanese Unexamined Patent Application Publication No. 2006-5164 discloses only a method for evaluating the surface configuration of an epitaxial wafer and does not disclose a concrete method for alleviating distortions on a back surface of the epitaxial wafer.
Under such circumstances, the present inventors found that distortions on a back surface of the epitaxial wafer can be alleviated by forming a silicon oxide film in advance on the back surface of a semiconductor wafer on which an epitaxial layer is to be grown, and have utilized this as a method for improving a manufacturing method for an epitaxial wafer.
Here, a lift pin used for attaching and detaching a semiconductor wafer or an epitaxial wafer (hereinafter may be collectively referred to simply as wafer) is embedded in a bottom face of a concave shaped wafer placement portion on a top face of the susceptor. The lift pin has a head portion having a larger diameter and is disposed such that the head portion is hung on a tapered side wall portion of a through hole provided on the bottom face of the wafer placement portion. If the susceptor is lowered and a lower portion of the lift pin contacts the bottom face of the reaction container, the lift pin is biased and the head portion thereof hits the back surface of the wafer, thereby lifting the wafer from the wafer placement portion.
As described above, the lift pin is a component required to detach the wafer from the wafer placement portion of the susceptor. However, the lift pin is generally formed of a material having a thermal conductivity different from that of the susceptor, leading to a nonuniform temperature distribution on a surface of a wafer placed on the susceptor. According to a result of a manufacturing test conducted by the present inventors, it was ascertained that SFQR (Site flatness Front side least sQuare fit Range), in other words a flatness, of an epitaxial wafer decreases in a case where, with such a nonuniform temperature distribution on the surface of the wafer, epitaxial growth is performed as described above by growing a silicon oxide film on the whole back surface of a semiconductor wafer. In this case, SFQR significantly decreases only in a site where the lift pin was present on the back surface of the epitaxial wafer. As described above, an epitaxial wafer with high flatness and high definition is required accompanying design rule miniaturization and the like. Therefore, such an epitaxial wafer, of which flatness is low in parts thereof, is a factor contributing to a lower yield in manufacturing of semiconductor devices.
The present invention is made in view of the abovementioned problems, and aims at providing a manufacturing method for an epitaxial wafer that can alleviate distortions on a back surface thereof due to sticking between a wafer and a susceptor, thereby preventing decrease in flatness of the epitaxial wafer due to presence of a lift pin.